The present subject matter relates in general to semiconductor power device technology, and in particular to structures and methods for forming shield contacts in shielded gate metal-oxide-semiconductor field effect transistors (MOSFETs).
A typical shielded gate MOSFET die includes an active region with an array of mesas and trenches forming active devices. Shield electrodes are disposed in a bottom portion of the trenches and gate electrodes are disposed in an upper portion of the trenches over the shield electrodes. The active devices are configured to conduct current in an ON-state. The active region is typically surrounded by an inactive interconnect region that is not intended to conduct current. The interconnect region is configured to provide electrical contacts to the gate and shield electrodes in the active region. Typically one or more stripes of conductive material in the interconnect region called gate runners make electrical contact with the gate electrodes in the active region. Each gate runner is electrically connected to a gate pad generally located in the interconnect region. Typically one or more stripes of conductive material called shield runners are disposed parallel to the gate runners in the interconnect region. The shield runners are isolated from the gate runners and make electrical contact with the shield electrodes in the active region. The shield runners are typically coupled to the source conductive layer or to a shield pad.
By positioning the gate and shield runners in the interconnect region, the area in the active region is preserved for active devices. This leads to an increase in gate and shield resistance, however, because contact to the gate and shield electrodes is along the edge of the die in the interconnect region. Thus, there is a need in the art for improved shielded gate MOSFETs with low gate and shield resistance.